US 12,250,819 B2
Semiconductor device and method for manufacturing semiconductor device
Shunpei Yamazaki, Tokyo (JP); Tatsuya Onuki, Kanagawa (JP); and Satoru Okamoto, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Appl. No. 17/623,301
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
PCT Filed Jun. 23, 2020, PCT No. PCT/IB2020/055892
§ 371(c)(1), (2) Date Dec. 28, 2021,
PCT Pub. No. WO2021/005435, PCT Pub. Date Jan. 14, 2021.
Claims priority of application No. 2019-125710 (JP), filed on Jul. 5, 2019; and application No. 2019-239500 (JP), filed on Dec. 27, 2019.
Prior Publication US 2022/0367509 A1, Nov. 17, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 43/27 (2023.01)
CPC H10B 43/27 (2023.02) 16 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first insulator comprising a first opening;
a first conductor comprising a second opening over the first insulator;
a second insulator comprising a third opening over the first conductor;
a third insulator provided along a first side surface of the first opening, a second side surface of the second opening, and a third side surface of the third opening;
an oxide provided along the first side surface, the second side surface, and the third side surface with the third insulator therebetween;
a second conductor provided at the first side surface with the third insulator and the oxide therebetween; and
a third conductor provided at the third side surface with the third insulator and the oxide therebetween,
wherein the oxide comprises a first region in the first opening, a second region in the second opening, and a third region in the third opening, and
wherein the second region has higher resistance than the first region and the third region.