| CPC H10B 41/35 (2023.02) | 20 Claims |
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1. A method of fabrication of a semiconductor device, comprising:
dividing a substrate into first and second regions;
forming a first recess to a first depth in the first region;
forming a non-volatile memory (NVM) transistor and a select transistor at least partly within the first recess, further comprising:
forming a non-volatile (NV) dielectric stack in the first recess, wherein the NV dielectric stack includes a blocking oxide disposed over a charge-trapping layer and a tunnel oxide;
performing at least one silicon oxide deposition process in an atomic layer deposition (ALD) tool to form a gate dielectric layer of the select transistor adjacent to the NV dielectric stack in the first recess;
performing an oxide removal process step to thin out a thickness of the blocking oxide of the NV dielectric stack;
forming a high-K dielectric layer overlying the blocking oxide and the gate dielectric layer respectively;
forming a sacrificial polysilicon gate over the high-K dielectric layers of the NV dielectric stack and the gate dielectric layer respectively; and
replacing the sacrificial polysilicon gates with metal gates.
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