| CPC H10B 41/35 (2023.02) [G11C 16/0483 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] | 20 Claims |

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1. A three-dimensional memory device, comprising:
a first-tier alternating stack of first insulating layers and first electrically conductive layers;
a second-tier alternating stack of second insulating layers and second electrically conductive layers that overlies the first-tier alternating stack;
a vertically alternating sequence of insulating plates and dielectric material plates located over the first-tier alternating stack and laterally surrounded by the second-tier alternating stack;
memory openings vertically extending through each layer within the first-tier alternating stack and the second-tier alternating stack;
memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective vertical stack of memory elements;
first contact via structures vertically extending through the vertically alternating sequence and contacting a respective one of the first electrically conductive layers; and
second contact via structures contacting a respective one of the second electrically conductive layers.
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