| CPC H10B 41/27 (2023.02) [H01L 29/40114 (2019.08); H01L 29/42324 (2013.01); H10B 41/35 (2023.02)] | 4 Claims |
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1. A semiconductor device comprising:
a gate structure including insulating layers and control gates, which are alternately stacked;
a channel layer penetrating the gate structure;
floating gates respectively located between the control gates and the channel layer;
first blocking patterns respectively located between the control gates and the floating gates;
a second blocking pattern located between the first blocking patterns and the floating gates and between the floating gates and the insulating layers, the second blocking pattern including a material with a dielectric constant that is lower than that of the first blocking patterns;
third blocking patterns respectively located between the first blocking patterns and the control gates, the third blocking patterns including a material with a dielectric constant that is lower than that of the first blocking patterns; and
metal patterns respectively located between the second blocking pattern and the floating gates and in direct contact with the floating gates,
wherein each of the floating gates overlaps each of the insulating layers without the first blocking patterns and the third blocking patterns intervening, and
wherein each of the control gates overlaps each of the insulating layers without the first blocking patterns and the third blocking patterns intervening.
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