US 12,250,810 B2
Small-area high-efficiency read-only memory (ROM) array and method for operating the same
Yu Ting Huang, Chu-Pei (TW); and Chi Pei Wu, Chu-Pei (TW)
Assigned to Yield Microelectronics Corp., Chu-pei (TW)
Filed by YIELD MICROELECTRONICS CORP., Chu-Pei (TW)
Filed on Mar. 20, 2023, as Appl. No. 18/186,278.
Claims priority of application No. 112103524 (TW), filed on Feb. 1, 2023.
Prior Publication US 2024/0260260 A1, Aug. 1, 2024
Int. Cl. H10B 41/00 (2023.01); G11C 17/12 (2006.01); H10B 20/00 (2023.01)
CPC H10B 20/363 (2023.02) [G11C 17/126 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A small-area high-efficiency read-only memory (ROM) array, comprising:
a plurality of parallel bit lines comprising a first bit line, a second bit line, a third bit line, and a fourth bit line adjacent to each other;
a plurality of parallel word common-source lines, arranged perpendicular to the bit lines, comprising a first word common-source line; and
a plurality of sub-memory arrays, wherein each of the plurality of sub-memory arrays is connected to four of the bit lines and one of the word common-source lines, and each of the plurality of sub-memory arrays comprises:
a first memory cell connected to the first bit line and the first word common-source line;
a second memory cell connected to the second bit line and the first word common-source line, wherein the first memory cell and the second memory cell are arranged adjacent to each other in a vertical direction;
a third memory cell connected to the third bit line and the first word common-source line, wherein the third memory cell and the first memory cell are arranged adjacent to each other in a horizontal direction; and
a fourth memory cell connected to the fourth bit line and the first word common-source line and arranged at a point where the vertical direction corresponding to the third memory cell intersects the horizontal direction corresponding to the second memory cell,
wherein the first memory cell, the second memory cell, the third memory cell, and the fourth memory cell are arranged between the first bit line and the fourth bit line,
wherein each of the first memory cell, the second memory cell, the third memory cell, and the fourth memory cell comprises a field-effect transistor (FET) with a drain, a source, and a gate,
wherein the FETs of the first memory cell, the second memory cell, the third memory cell, and the fourth memory cell share a dielectric layer,
wherein the dielectric layer partially overlaps the sources and the gates of the FETs, and
wherein the source and the gate of each FET of the sub-memory array are each connected to the first word common-source line.