US 12,250,809 B2
One-time programmable memory cell and memory thereof
Dan Ning, Sichuan (CN); and Yulong Wang, Sichuan (CN)
Assigned to Chengdu Analog Circuit Technology Inc., Chengdu (CN)
Filed by Chengdu Analog Circuit Technology Inc., Sichuan (CN)
Filed on Apr. 17, 2023, as Appl. No. 18/301,473.
Claims priority of application No. 202210724399.2 (CN), filed on Jun. 23, 2022; and application No. 202211053131.7 (CN), filed on Aug. 31, 2022.
Prior Publication US 2023/0422494 A1, Dec. 28, 2023
Int. Cl. G11C 17/16 (2006.01); H01L 23/525 (2006.01); H10B 20/25 (2023.01)
CPC H10B 20/25 (2023.02) [G11C 17/16 (2013.01); H01L 23/5252 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A one-time programmable memory cell, comprising:
a selection transistor and a gate capacitor, which are connected in series and located in a substrate, the substrate comprising an active region and an isolation region;
wherein the gate capacitor comprises:
a gate,
a gate oxide layer between the gate and the substrate, and
an ion-doped region beneath the gate oxide layer, the ion-doped region being located in the active region in the substrate and overlapping with a part of a lower surface of the gate oxide layer;
wherein a part of the lower surface of the gate oxide layer that does not overlap with the ion-doped region completely overlaps with the isolation region in the substrate, and the ion-doped region and the isolation region are seamlessly adjacent to each other in the substrate beneath the gate oxide layer.