US 12,250,804 B2
SRAM cell layout including arrangement of multiple active regions and multiple gate regions
Shafquat Jahan Ahmed, Greater Noida (IN); and Dhori Kedar Janardan, Ghaziabad (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Aug. 23, 2023, as Appl. No. 18/454,471.
Application 18/454,471 is a continuation of application No. 17/118,372, filed on Dec. 10, 2020, granted, now 11,758,707.
Claims priority of provisional application 62/950,761, filed on Dec. 19, 2019.
Prior Publication US 2023/0403838 A1, Dec. 14, 2023
Int. Cl. H10B 10/00 (2023.01)
CPC H10B 10/12 (2023.02) [H10B 10/18 (2023.02)] 18 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a first memory cell including a first pair of cross-coupled inverters including:
a first transistor that includes a first active region extending along a first axis and a first gate region extending transversely to the first axis and overlaying the first active region;
a second transistor that includes a second gate region extending transversely to the first axis and overlaying the first active region, the second gate region being spaced apart from the first gate region along the first axis; and
a third transistor that includes a third gate region extending transversely to the first axis and overlying the first active region;
a second memory cell including a second active region spaced from the first active region; and
a third memory cell including a third active region spaced from the first active region, wherein the first active region extends into the second memory cell and the third memory cell, the second active region extends from the second memory cell into the first memory cell, and the third active region extends from the third memory cell into the first memory cell.