| CPC H04W 74/085 (2013.01) [H04W 76/27 (2018.02)] | 20 Claims |

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1. A baseband processor, comprising:
a memory interface and a communication interface; and
processing circuitry communicatively coupled to the memory interface and the communication interface and, when executing instructions received from the memory interface, performs operations comprising:
generating a Random Access Channel (RACH) preamble in response to a determination to perform a Radio Resource Control (RRC) inactive data transmission in a RRC inactive state;
providing uplink (UL) data to the communication interface for the RRC inactive data transmission, wherein the RRC inactive data transmission comprises a medium access control control element (MAC CE) with an inactive radio network temporary identifier (I-RNTI), or a truncated I-RNTI (I-RNTI/truncated I-RNTI), or the RRC inactive data transmission is scrambled based on the I-RNTI/truncated I-RNTI;
starting a contention resolution (CR) timer after the RRC inactive data transmission, wherein the CR timer is set to end at a CR duration limit; and
receiving, before the CR timer ends at the CR duration limit, a RACH message in response to the RRC inactive data transmission, wherein the RACH message comprises at least one of an uplink (UL) grant or a downlink (DL) assignment scrambled by the I-RNTI/truncated I-RNTI, or the RACH message comprises a DL assignment based on a temporary cell radio network temporary identifier (T-C-RNTI) that is comprised in the MAC CE.
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