US 12,250,481 B2
Image sensor with stacked CCD and CMOS architecture
Xianmin Yi, Menlo Park, CA (US); and Alexander Lu, San Jose, CA (US)
Assigned to FAIRCHILD IMAGING, INC., Wilmington, DE (US)
Filed by Fairchild Imaging, Inc., San Jose, CA (US)
Filed on Feb. 7, 2023, as Appl. No. 18/106,581.
Prior Publication US 2024/0267652 A1, Aug. 8, 2024
Int. Cl. H04N 25/75 (2023.01); H01L 27/146 (2006.01); H04N 25/778 (2023.01); H04N 25/78 (2023.01)
CPC H04N 25/75 (2023.01) [H01L 27/14636 (2013.01); H01L 27/14643 (2013.01); H04N 25/778 (2023.01); H04N 25/78 (2023.01)] 16 Claims
OG exemplary drawing
 
1. An image sensor, comprising:
an array of image sensing pixels on a first substrate, wherein at least one image sensing pixel comprises a gate over the first substrate, and wherein an adjacent gate from an adjacent image sensing pixel partially overlaps with the gate of the at least one image sensing pixel;
a conductive structure on the first substrate and coupled to a given pixel of the array of image sensing pixels;
a readout circuit coupled to the conductive structure, wherein the readout circuit comprises one or more metal oxide semiconductor (MOS) devices on a second substrate different from the first substrate; and
a dielectric layer between the gate of the at least one image sensing pixel and the first substrate, wherein the dielectric layer has a thickness between about 10 nm and about 100 nm.