US 12,250,288 B2
Information processing device, information processing method, and program
Takashi Horiguti, Kanagawa (JP); and Yutaka Nakada, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Appl. No. 17/794,328
Filed by Sony Semiconductor Solutions Corporation, Kanagawa (JP)
PCT Filed Jan. 18, 2021, PCT No. PCT/JP2021/001416
§ 371(c)(1), (2) Date Jul. 21, 2022,
PCT Pub. No. WO2021/153301, PCT Pub. Date Aug. 5, 2021.
Claims priority of application No. 2020-014934 (JP), filed on Jan. 31, 2020.
Prior Publication US 2023/0046212 A1, Feb. 16, 2023
Int. Cl. H04L 69/22 (2022.01); H04N 21/434 (2011.01); H04N 21/4425 (2011.01)
CPC H04L 69/22 (2013.01) [H04N 21/4343 (2013.01); H04N 21/4425 (2013.01)] 17 Claims
OG exemplary drawing
 
7. An information processing device comprising:
a memory storing instructions, and
at least one processor configured to execute the instructions to perform operations comprising:
performing correction on a payload length obtained on a basis of data of headers of second packets included in a first packet;
calculating a packet length of the second packets by using a header length of the headers of the second packets and the payload length after performing the correction;
detecting a first protocol error based on a difference between a head position of the second packet at a head specified by data of a header of the first packet and the head position of the second packet at the head specified by the packet length of the second packet immediately before the second packet at the head, among the second packets included in the second packet; and
detecting a second protocol error based on a packet type detected by data from a head position of the second packet that is next specified by the packet length of the second packet.