US 12,250,072 B2
Information processing device, communication system, and information processing method to increase frequency utilization efficiency
Hiroki Matsuda, Tokyo (JP); Ren Sugai, Tokyo (JP); and Ryota Kimura, Tokyo (JP)
Assigned to SONY GROUP CORPORATION, Tokyo (JP)
Appl. No. 17/998,669
Filed by SONY GROUP CORPORATION, Tokyo (JP)
PCT Filed May 19, 2021, PCT No. PCT/JP2021/018921
§ 371(c)(1), (2) Date Nov. 13, 2022,
PCT Pub. No. WO2021/241345, PCT Pub. Date Dec. 2, 2021.
Claims priority of application No. 2020-092718 (JP), filed on May 27, 2020.
Prior Publication US 2023/0198664 A1, Jun. 22, 2023
Int. Cl. H04L 1/00 (2006.01); G06F 3/00 (2006.01); H04L 1/06 (2006.01)
CPC H04L 1/0057 (2013.01) [H04L 1/0041 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An information processing device, comprising:
a first encoding processing unit configured to perform a first error correction encoding process in which a plurality of bit sequences is output; and
a determination unit configured to:
divide the plurality of bit sequences into a first bit sequence group and a second bit sequence group; and
determine that transmission of the first bit sequence group and the second bit sequence group are through different propagation paths, wherein
the second bit sequence group is transmitted based on a quality of a propagation path of the different propagation paths through which the first bit sequence group is transmitted, and
the first bit sequence group is decodable without a first error correction decoding process corresponding to the first error correction encoding process, and the second bit sequence group is for the first error correction decoding process.