US 12,250,005 B2
Error correction systems and methods
Gregory Alan Bryant, Raleigh, NC (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Jun. 16, 2023, as Appl. No. 18/336,697.
Prior Publication US 2024/0421833 A1, Dec. 19, 2024
Int. Cl. H03M 13/15 (2006.01); G06F 7/523 (2006.01); H03M 13/29 (2006.01)
CPC H03M 13/1575 (2013.01) [G06F 7/523 (2013.01); H03M 13/2942 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic circuit for correcting data errors comprising:
a syndrome generator to receive data comprising a plurality of parity bits and generate a plurality of successive odd syndromes;
a coefficient generator, configured to receive the plurality of successive odd syndromes and combine the syndromes to produce a plurality of coefficients;
a multibit error detector configured to receive the coefficients, wherein the coefficients are applied to a plurality of digital values, wherein the digital values applied to the plurality of coefficients generates a first bit error vector;
an error correction circuit configured to combine the first bit error vector with the data, wherein the first bit error vector is combined with the data to correct one or more bit errors in the data
a single bit error detector configured to receive a first syndrome of the plurality of successive odd syndromes and produce a second bit error vector, wherein the error correction circuit combines the second bit error vector with the data to correct one bit error in the data; and
the error correction circuit configured to combine the first bit error vector with the data, wherein the first bit error vector is combined with the data to correct one or more bit errors in the data, wherein one of the plurality of coefficients selects between the first bit error vector and the second bit error vector in the error correction circuit.