US 12,250,002 B2
Analog digital converter
Po-Hua Chen, Changhua County (TW); Yu-Yee Liow, Hsinchu County (TW); Chih-Wei Wu, Kaohsiung (TW); Wen-Hong Hsu, Hsinchu (TW); Hsuan-Chih Yeh, New Taipei (TW); and Pei-Wen Sun, Hsinchu County (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsinchu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsinchu (TW)
Filed on Mar. 28, 2023, as Appl. No. 18/127,262.
Claims priority of application No. 112108888 (TW), filed on Mar. 10, 2023.
Prior Publication US 2024/0305310 A1, Sep. 12, 2024
Int. Cl. H03M 1/46 (2006.01)
CPC H03M 1/46 (2013.01) 7 Claims
OG exemplary drawing
 
1. A successive-approximation register (SAR) analog digital converter (ADC) comprising:
a sample-hold circuit sampling an input voltage based on a system clock to generate a sample-hold output signal;
a digital analog converter (DAC) generating a DAC output signal;
a comparator coupled to the sample-hold circuit and the DAC, the comparator comparing the sample-hold output signal with the DAC output signal to generate a comparing output signal;
a SAR combinational digital circuit group;
a multiplexer circuit coupled to the DAC and the SAR combinational digital circuit group; and
a plurality of registers coupled to the comparator, the SAR combinational digital circuit group and the multiplexer circuit, wherein the comparing output signal from the comparator is registered in the registers as a plurality of register output signals, the registers output the register output signals as an output signal of the SAR ADC,
wherein
the SAR combinational digital circuit group generates a plurality of first SAR output signals and a plurality of second SAR output signals based on the register output signals,
the SAR combinational digital circuit group includes a first SAR combinational digital circuit and a second SAR combinational digital circuit, the first SAR combinational digital circuit generates the first SAR output signals based on the register output signals, the second SAR combinational digital circuit generates the second SAR output signals based on the register output signals,
the multiplexer circuit selects the first SAR output signals or the second SAR output signals as a plurality of multiplexer output signals under control of the register output signals and sends the plurality of multiplexer output signals to the DAC;
a capacitor coupling relationship of the DAC is controlled by the multiplexer output signals.