US 12,249,996 B2
Counter design for a time-to-digital converter (TDC)
Manikanta Sakalabhaktula, Bangalore (IN); Debasish Behera, Bangalore (IN); Raja Prabhu J, Bangalore (IN); Girisha Angadi Basavaraja, Bangalore (IN); Nandakishore Palla, Bangalore (IN); Chandrasekhar BG, Bangalore (IN); and Sudarshan Varadarajan, Bangalore (IN)
Assigned to Shaoxing Yuanfang Semiconductor Co., Ltd., Zhejiang (CN)
Filed by Shaoxing Yuanfang Semiconductor Co., Ltd., Shaoxin (CN)
Filed on May 10, 2022, as Appl. No. 17/662,662.
Claims priority of application No. 202141044473 (IN), filed on Sep. 30, 2021.
Prior Publication US 2023/0106659 A1, Apr. 6, 2023
Int. Cl. H03L 7/085 (2006.01); G04F 10/00 (2006.01); H03L 7/081 (2006.01)
CPC H03L 7/085 (2013.01) [G04F 10/005 (2013.01); H03L 7/081 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A time-to-digital converter (TDC) comprising:
a counter to generate a sequence of counts representing a number of transitions of interest of a first clock signal, said counter comprising a first sub-counter and a second sub-counter, said first sub-counter comprising a first set of flip-flops and said second sub-counter comprising a second set of flip-flops,
wherein said first set of flip-flops are coupled in a first series with an output of each flip-flop in said first series being coupled to a clock input of immediately next flip-flop in said first series to together operate as an asynchronous circuit,
wherein transitions of said second set of flip-flops are driven by a common clock to together operate as a synchronous circuit, wherein said second set of flip-flops are coupled in a second series, with an output of each flip-flop in said second series being coupled to a data input of immediately next flip-flop in said second series,
wherein said first set of flip-flops and said second set of flip-flops respectively generate a first set of bits and a second set of bits of each of said sequence of counts; and
a digital core to process a pair of counts of said sequence.