US 12,249,993 B2
Asymmetric NAND gate circuit, clock gating cell and integrated circuit including the same
Byounggon Kang, Suwon-si (KR); and Dalhee Lee, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Sep. 26, 2023, as Appl. No. 18/373,017.
Claims priority of application No. 10-2022-0137767 (KR), filed on Oct. 24, 2022; and application No. 10-2023-0019542 (KR), filed on Feb. 14, 2023.
Prior Publication US 2024/0137012 A1, Apr. 25, 2024
Prior Publication US 2024/0235533 A9, Jul. 11, 2024
Int. Cl. H03K 3/037 (2006.01); G06F 1/08 (2006.01); H03K 3/012 (2006.01); H03K 19/20 (2006.01)
CPC H03K 3/037 (2013.01) [G06F 1/08 (2013.01); H03K 19/20 (2013.01); H03K 3/012 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A clock gating cell comprising:
an inverter circuit configured to generate an inverted clock signal by inverting a clock signal;
a first control circuit configured to receive the inverted clock signal, an enable signal, and a scan enable signal, and output a first internal signal at a first node;
a second control circuit configured to receive the first internal signal, the clock signal, the enable signal, and the scan enable signal, and output a second internal signal at a second node; and
an output driver configured to receive the second internal signal, and output an output clock signal to an output node and a third internal signal to a third node,
wherein the first control circuit and the second control circuit are configured to receive the third internal signal at the third node.