US 12,249,992 B2
D flip-flop, processor including the d flip-flop, and computing apparatus
Wenbo Tian, Guangdong (CN); Chuan Gong, Guangdong (CN); Zhijun Fan, Guangdong (CN); Zuoxing Yang, Guangdong (CN); and Haifeng Guo, Guangdong (CN)
Assigned to SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD., Guangdong (CN)
Appl. No. 18/038,774
Filed by SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD., Guangdong (CN)
PCT Filed Mar. 6, 2023, PCT No. PCT/CN2023/079832
§ 371(c)(1), (2) Date May 25, 2023,
PCT Pub. No. WO2023/207339, PCT Pub. Date Nov. 2, 2023.
Claims priority of application No. 202210455795.X (CN), filed on Apr. 28, 2022.
Prior Publication US 2024/0364316 A1, Oct. 31, 2024
Int. Cl. H03K 3/037 (2006.01); H03K 3/012 (2006.01)
CPC H03K 3/037 (2013.01) [H03K 3/012 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A D flip-flop comprising:
an input stage configured to receive a flip-flop input;
an output stage configured to output a flip-flop output;
an intermediate node disposed between an output of the input stage and an input of the output stage, wherein the output stage is configured to receive a signal at the intermediate node as an input;
an intermediate stage configured to receive an output of the input stage and provide the output to the intermediate node; and
a feedback stage configured to receive the flip-flop output and provide a feedback to the intermediate node,
wherein the feedback stage assumes a logic-high state, a logic-low state, and a high-impedance state,
wherein a potential at the intermediate node is maintained such that a use of a high-threshold transistor as a transistor connected to the intermediate node is avoided in the D flip-flop, and a threshold of the transistor connected to the intermediate node in the D flip-flop is substantially identical to thresholds of all other transistors in the D flip-flop.