US 12,249,991 B2
Clock generator circuit for near field communication device
Laurent Jean Garcia, Le Champ Pres Froges (FR); and Marc Houdebine, Crolles (FR)
Assigned to STMicroelectronics France, Montrouge (FR)
Filed by STMicroelectronics France, Montrouge (FR)
Filed on Jun. 30, 2023, as Appl. No. 18/345,726.
Claims priority of application No. 2206796 (FR), filed on Jul. 5, 2022.
Prior Publication US 2024/0014809 A1, Jan. 11, 2024
Int. Cl. H03K 3/03 (2006.01); H03K 5/1252 (2006.01)
CPC H03K 3/0315 (2013.01) [H03K 5/1252 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A clock generator circuit comprising:
an oscillator circuit configured to generate a clock signal at a given frequency dependent on a supply current to the oscillator circuit;
a bias circuit configured to control the supply current of the oscillator circuit, the bias circuit comprising:
a current mirror comprising a reference transistor and a set of copy transistors that are programmable according to a digital word received as an input of the bias circuit;
a third transistor having a source connected to a cold spot, a drain, and a gate connected to the drain of the third transistor;
a fourth transistor having a source connected to the drain of the third transistor, a drain, and a gate connected to the drain of the fourth transistor; and
a cascode transistor having a source connected to a drain of at least one of the copy transistors, a drain, and a gate connected to the gate of the fourth transistor, wherein the gates of the fourth transistor and the cascode transistor are thicker than the gates of the reference transistor, each copy transistor, and the third transistor.