US 12,249,990 B1
Apparatus and method for wideband multi-phase clock generation
Jacob Pike, Ottawa (CA); Naim Ben-Hamida, Ottawa (CA); Jerry Yee-Tung Lam, Markham (CA); Euhan Chong, Kanata (CA); and David Berton, Ottawa (CA)
Assigned to CIENA CORPORATION, Hanover, MD (US)
Filed by CIENA CORPORATION, Hanover, MD (US)
Filed on Nov. 15, 2023, as Appl. No. 18/509,910.
Int. Cl. H03K 21/17 (2006.01); H03K 3/017 (2006.01); H03K 21/40 (2006.01); H03L 7/08 (2006.01)
CPC H03K 3/017 (2013.01) [H03K 21/17 (2013.01); H03K 21/40 (2013.01); H03L 7/0807 (2013.01)] 20 Claims
OG exemplary drawing
 
17. A method for creating a deterministic starting state of a ring-based injection locked frequency divider in an inner clock generation circuit, comprising:
implementing a reset gate on an output of each tri-state inverter in a ring of tri-state inverters;
implementing a reset circuit comprising one or more selectable flip-flops;
applying a reset signal to each reset gate, wherein the reset gate forces the output of the tri-state inverter to a starting state; and
applying a phase select signal to the reset circuit, wherein the reset circuit inverts the output of the tri-state inverter.