US 12,249,989 B1
Four-phase clock buffer of twenty-five percent duty cycle
Chia-Liang (Leon) Lin, Fremont, CA (US)
Assigned to Realtek Semiconductor Corp., Hsinchu (TW)
Filed by Realtek Semiconductor Corp., Hsinchu (TW)
Filed on Aug. 25, 2023, as Appl. No. 18/455,676.
Int. Cl. H03K 3/017 (2006.01); H03K 3/356 (2006.01)
CPC H03K 3/017 (2013.01) [H03K 3/356113 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A four-phase (hereafter 4-phase) clock buffer comprising:
a first p-channel metal oxide semiconductor transistor (hereafter PMOST), a second PMOST, a third PMOST, and a fourth PMOST configured in a common-source ring topology to dispatch a first phase, a second phase, a third phase, and a fourth phase of a 4-phase output clock, respectively; and,
a first n-channel metal oxide semiconductor transistor (hereafter NMOST), a second NMOST, a third NMOST, and a fourth NMOST configured in a common-source topology to control the first phase, the second phase, the third phase, and the fourth phase of the 4-phase output clock, in response to a first phase, a second phase, a third phase, and a fourth phase of a 4-phase input clock, respectively.