US 12,249,986 B2
Level converter circuit
Etienne Cesar, Voreppe (FR)
Assigned to STMICROELECTRONICS (GRENOBLE 2) SAS, Grenoble (FR)
Filed by STMicroelectronics (Grenoble 2) SAS, Grenoble (FR)
Filed on Aug. 3, 2023, as Appl. No. 18/364,950.
Application 18/364,950 is a continuation of application No. 17/382,794, filed on Jul. 22, 2021, granted, now 11,757,448.
Claims priority of application No. 2008274 (FR), filed on Aug. 4, 2020.
Prior Publication US 2023/0378957 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 19/0185 (2006.01); H03K 3/011 (2006.01); H03K 19/003 (2006.01)
CPC H03K 19/018521 (2013.01) [H03K 3/011 (2013.01); H03K 19/00369 (2013.01); H03K 19/00384 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a level converter circuit comprising:
a first transistor, a gate of the first transistor being configured to receive a current proportional to a temperature; and
a power supply circuit configured to supply the current proportional to the temperature, the power supply circuit being coupled with the gate of the first transistor, the power supply circuit comprising a first current mirror circuit and a second current mirror circuit.