US 12,249,957 B2
Self-biased, closed loop, low current free running oscillator
Divya Tripathi, Noida (IN); Sadique Mohammad Iqbal, Karimganj (IN); Anubhav Srivastava, Gorakhpur (IN); Krishna Thakur, GautamBudh Nagar (IN); Pragya Priya Malakar, Chandler, AZ (US); and John Pigott, Phoenix, AZ (US)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Apr. 6, 2023, as Appl. No. 18/296,539.
Claims priority of application No. 202211056103 (IN), filed on Sep. 30, 2022.
Prior Publication US 2024/0113660 A1, Apr. 4, 2024
Int. Cl. H03L 7/02 (2006.01); H03B 5/04 (2006.01); H03B 5/24 (2006.01)
CPC H03B 5/04 (2013.01) [H03B 5/24 (2013.01); H03L 7/02 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A free running oscillator clock generator, comprising:
a current mode comparator connected to a trimming resistor and configured to compare an internally generated voltage reference VREF signal to a voltage feedback signal VFB, where the current mode comparator comprises a common gate amplifier connected to a current mirror circuit in a negative self-biased closed loop to generate a control current signal;
a current controlled oscillator connected to receive the control current signal and configured to produce an output clock signal having a clock frequency based on the control current signal; and
a frequency-to-voltage converter connected in a feedback path to receive the output clock signal and configured to produce the voltage feedback signal VFB for input to the current mode comparator,
wherein the clock frequency of the output clock signal is tuned to a nominal locked value by the trimming resistor.