US 12,249,909 B2
Power supply noise reduction by current cancellation circuit
Meei-Ling Chiang, Cupertino, CA (US); Khaled M. Alashmouny, Sunnyvale, CA (US); and Zhi Hu, San Jose, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Aug. 25, 2022, as Appl. No. 17/895,587.
Prior Publication US 2024/0072651 A1, Feb. 29, 2024
Int. Cl. H02M 1/15 (2006.01); H02M 1/44 (2007.01); H02M 3/156 (2006.01)
CPC H02M 1/44 (2013.01) [H02M 1/15 (2013.01); H02M 3/1566 (2021.05)] 20 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a current source comprising a transistor having a first terminal electrically directly coupled to a voltage supply and configured to generate a first current with a first current rate-of-change during a time interval, wherein the transistor has a second terminal directly coupled to a ground signal; and
a load circuit having a terminal electrically coupled in parallel to the first terminal of the transistor and to the voltage supply and configured to generate a second current with a second current rate-of-change during the time interval, wherein the second current rate-of-change is based on an inverse of the first current rate-of-change.