US 12,249,748 B2
Edge capacitive coupling for quantum chips
Muir Kumph, Croton on Hudson, NY (US); Oliver Dial, Yorktown Heights, NY (US); John Michael Cotte, New Fairfield, CT (US); and David Abraham, Croton, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Sep. 23, 2022, as Appl. No. 17/935,023.
Prior Publication US 2024/0104414 A1, Mar. 28, 2024
Int. Cl. H01P 5/02 (2006.01); G06N 10/40 (2022.01); H01P 11/00 (2006.01); H01R 12/72 (2011.01); H02J 50/05 (2016.01)
CPC H01P 5/028 (2013.01) [G06N 10/40 (2022.01); H01P 5/02 (2013.01); H01P 11/003 (2013.01); H01R 12/721 (2013.01); H02J 50/05 (2016.02)] 22 Claims
OG exemplary drawing
 
2. A quantum computing chip device, comprising:
a first chip including a first signal line including a distal end positioned proximate to or on an edge of the first chip, and a proximal end positioned away from the edge of the first chip; and
a second chip including a second signal line including a distal end positioned proximate to or on an edge of the second chip and a proximal end positioned away from the edge of the second chip,
wherein the distal end of the first signal line is spaced from the edge of the first chip by a substrate material;
wherein the second signal line of the second chip is disposed in alignment for a capacitive bus connection to the first signal line of the first chip; and
wherein the first signal line and the second signal line are configured to conduct a signal.