US 12,249,659 B2
2D materials with inverted gate electrode for high density 3D stacking
Mark I. Gardner, Albany, NY (US); and H. Jim Fulford, Albany, NY (US)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on Jan. 18, 2022, as Appl. No. 17/578,397.
Prior Publication US 2023/0231057 A1, Jul. 20, 2023
Int. Cl. H01L 27/12 (2006.01); H01L 21/8234 (2006.01); H01L 29/792 (2006.01); H10B 43/27 (2023.01)
CPC H01L 29/7926 (2013.01) [H01L 21/823431 (2013.01); H01L 27/1225 (2013.01); H10B 43/27 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a gate electrode;
a gate dielectric layer disposed on the gate electrode;
a two-dimensional (2D) semiconductor layer disposed on the gate dielectric layer;
a source electrode extending through the gate dielectric layer to the 2D semiconductor layer;
a drain electrode extending through the gate dielectric layer and to the 2D semiconductor layer; and
a gate contact extending through the 2D semiconductor layer and the gate dielectric layer to the gate electrode.