US 12,249,656 B2
Transistor, integrated circuit, and manufacturing method of transistor
Marcus Johannes Henricus Van Dal, Linden (BE)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 16, 2024, as Appl. No. 18/665,572.
Application 18/665,572 is a continuation of application No. 18/165,936, filed on Feb. 8, 2023, granted, now 12,021,154.
Application 18/165,936 is a continuation of application No. 17/099,800, filed on Nov. 17, 2020, granted, now 11,605,740, issued on Mar. 14, 2023.
Claims priority of provisional application 63/030,929, filed on May 28, 2020.
Prior Publication US 2024/0304730 A1, Sep. 12, 2024
Int. Cl. H01L 29/786 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01); H01L 29/41 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01)
CPC H01L 29/78696 (2013.01) [H01L 27/1207 (2013.01); H01L 29/0665 (2013.01); H01L 29/413 (2013.01); H01L 29/42392 (2013.01); H01L 29/66969 (2013.01); H01L 29/7853 (2013.01); H10B 61/22 (2023.02); H10B 63/30 (2023.02); H01L 29/7869 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A transistor, comprising:
a first gate structure comprising metallic nanosheets, wherein each of the metallic nanosheets comprises a top surface, a bottom surface opposite to the top surface, and sidewalls connecting the top surface and the bottom surface;
a channel layer surrounding the top surfaces, the bottom surfaces, and the sidewalls of the metallic nanosheets; and
source/drain contacts electrically connected to the channel layer, wherein a portion of the channel layer is located between the source/drain contacts and the metallic nanosheets.