US 12,249,654 B2
Semiconductor device
Yohei Yamaguchi, Tokyo (JP); Yuichiro Hanyu, Tokyo (JP); and Hiroki Hidaka, Tokyo (JP)
Assigned to Japan Display Inc., Tokyo (JP)
Filed by Japan Display Inc., Tokyo (JP)
Filed on Aug. 10, 2023, as Appl. No. 18/447,400.
Application 18/447,400 is a continuation of application No. 17/510,534, filed on Oct. 26, 2021, granted, now 11,764,305.
Application 17/510,534 is a continuation of application No. 16/735,800, filed on Jan. 7, 2020, granted, now 11,189,734, issued on Nov. 30, 2021.
Claims priority of application No. 2019-002939 (JP), filed on Jan. 10, 2019.
Prior Publication US 2023/0387319 A1, Nov. 30, 2023
Int. Cl. H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 27/12 (2006.01); H01L 29/423 (2006.01); H10K 59/123 (2023.01); H10K 59/126 (2023.01)
CPC H01L 29/7869 (2013.01) [H01L 21/02266 (2013.01); H01L 21/02554 (2013.01); H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 27/1251 (2013.01); H01L 29/42384 (2013.01); H01L 29/78648 (2013.01); H01L 29/78696 (2013.01); H10K 59/126 (2023.02)] 4 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
an oxide semiconductor layer;
a gate electrode opposing the oxide semiconductor layer;
a gate insulating layer between the oxide semiconductor layer and the gate electrode;
a first insulating layer covering the oxide semiconductor layer;
an oxide layer;
a first conductive layer above the first insulating layer; and
a first electrode arranged above the oxide semiconductor layer and electrically connecting with the oxide semiconductor layer,
wherein
the oxide layer is arranged between the first insulating layer and the first conductive layer, and directly contacting the first insulating layer and the first conductive layer,
the first insulating layer have a first opening,
the first insulating layer directly contacts the oxide semiconductor layer,
the oxide layer has a second opening overlapping the first opening in a plan view,
the first conductive layer is arranged in the first opening and the second opening and directly contacts the first electrode at a bottom part of the first opening,
the gate electrode is arranged below the oxide semiconductor layer,
the oxide layer does not overlap the oxide semiconductor layer and the gate electrode, and
the first insulating layer is exposed from the oxide layer in a region not overlapping the first conductive layer in a plane view.