| CPC H01L 29/7827 (2013.01) [H01L 29/0847 (2013.01); H01L 29/41741 (2013.01); H01L 29/41775 (2013.01); H01L 29/42356 (2013.01); H01L 29/66553 (2013.01); H01L 29/66666 (2013.01)] | 20 Claims |
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1. A semiconductor device, comprising:
a first impurity region on a substrate;
a channel pattern protruding from an upper surface of the substrate, the channel pattern extending in a first direction substantially parallel to the upper surface of the substrate;
a second impurity region on the channel pattern, the second impurity region covering an entire upper surface of the channel pattern;
a gate structure on a sidewall of the channel pattern and the substrate adjacent to the channel pattern;
a first contact pattern on the second impurity region, the first contact pattern comprising a first barrier pattern that contacts the second impurity region, and a first metal pattern;
a second contact pattern that is electrically connected to the gate structure, the second contact pattern comprising a second metal pattern and a second barrier layer formed on sidewalls and a bottom of the second metal pattern; and
a spacer between the first contact pattern and the second contact pattern, the spacer contacting the first barrier pattern, the second barrier pattern, and the first metal pattern,
wherein the second contact pattern has four sides,
wherein the spacer surrounds the four sides of the second contact pattern in plan view,
wherein three sides of the four sides of the second contact pattern face the first contact pattern, and
wherein the first contact pattern surrounds the three sides of the second contact pattern in plan view.
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