US 12,249,646 B2
Double-diffused metal-oxide-semiconductor transistor including a recessed dielectric
Thomas S. Chung, Kissimmee, FL (US); Chung C. Kuo, Manchester, NH (US); Maxim Klebanov, Palm Coast, FL (US); and Sundar Chetlur, Frisco, TX (US)
Assigned to Allegro MicroSystems, LLC, Manchester, NH (US)
Filed by Allegro MicroSystems, LLC, Manchester, NH (US)
Filed on Mar. 15, 2022, as Appl. No. 17/695,029.
Prior Publication US 2023/0299195 A1, Sep. 21, 2023
Int. Cl. H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01)
CPC H01L 29/7816 (2013.01) [H01L 29/0634 (2013.01); H01L 29/0852 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A method comprising:
forming a double-diffused metal oxide semiconductor (DMOS) comprising:
depositing a first silicon nitride on a well;
depositing a first photoresist on the first silicon nitride;
using a first photolithographic process to remove portions of the first photoresist to expose at least one portion of the first silicon nitride;
performing a first etching of the first silicon nitride and the well;
depositing a first dielectric on a portion of the well etched by the first etching;
removing the first silicon nitride;
depositing a second silicon nitride on the well and an epitaxial layer;
depositing a second photoresist on the second silicon nitride;
using a second photolithographic process to remove portions of the second photoresist to expose at least one portion of the second silicon nitride;
performing a second etching of the second silicon nitride, the well, and the epitaxial layer; and
depositing a second dielectric on a portion of the well and the epitaxial layer etched by the second etching, wherein the second dielectric is in direct contact with the first dielectric.