US 12,249,644 B2
Enhancement-mode high-electron-mobility transistor
Matthieu Nongaillard, Grenoble (FR); and Thomas Oheix, Grenoble (FR)
Assigned to STMICROELECTRONICS INTERNATIONAL N.V., Geneva (CH)
Appl. No. 17/058,117
Filed by STMicroelectronics International N.V., Geneva (CH)
PCT Filed May 7, 2019, PCT No. PCT/FR2019/051041
§ 371(c)(1), (2) Date Nov. 23, 2020,
PCT Pub. No. WO2019/224448, PCT Pub. Date Nov. 28, 2019.
Claims priority of application No. 1854221 (FR), filed on May 22, 2018.
Prior Publication US 2021/0202728 A1, Jul. 1, 2021
Int. Cl. H01L 29/778 (2006.01); H01L 29/10 (2006.01); H01L 29/20 (2006.01)
CPC H01L 29/7786 (2013.01) [H01L 29/1066 (2013.01); H01L 29/2003 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An enhancement-mode high-electron-mobility transistor, comprising:
a structure having a first layer and a second layer of III-N-type semiconductor materials;
a source electrode and a drain electrode, each in electrical contact with the structure;
a gate electrode on the structure, between the source electrode and the drain electrode, the gate electrode having a first surface;
a bar under the gate electrode along a first direction, the bar including:
a n-type gallium nitride layer in the first layer, the n-type gallium nitride layer having a first face transverse to a second face;
a p-type gallium nitride layer directly on the n-type gallium nitride layer along the first direction; and
a PN junction at the interface of the n-type gallium nitride layer and the p-type gallium nitride layer;
an insulating layer between the gate electrode and the bar, the insulating layer having a first surface opposite a second surface along the first direction, the first surface of the gate electrode being between the first surface of the insulating layer and the second surface of the insulating layer along the first direction; and
a dielectric layer covering the first face and the second face of the n-type gallium nitride layer.