US 12,249,643 B2
Stacked planar field effect transistors with 2D material channels
Andrew Gaul, Halfmoon, NY (US); Julien Frougier, Albany, NY (US); Ruilong Xie, Niskayuna, NY (US); Andrew M. Greene, Slingerlands, NY (US); and Christopher J. Waskiewicz, Rexford, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Sep. 23, 2021, as Appl. No. 17/482,940.
Prior Publication US 2023/0093343 A1, Mar. 23, 2023
Int. Cl. H01L 29/76 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/24 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/7606 (2013.01) [H01L 21/02568 (2013.01); H01L 21/0259 (2013.01); H01L 29/0665 (2013.01); H01L 29/24 (2013.01); H01L 29/42392 (2013.01); H01L 29/66969 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
18. A method of forming a stacked device, comprising:
forming one or more stacks of alternating sacrificial layers and bridging layers on a substrate;
removing the sacrificial layers to expose opposite sides of the bridging layers;
converting the bridging layers to dielectric support bridges;
forming a first two-dimensional (2D) channel layer on a first side of the exposed surfaces of the dielectric support bridges;
forming a first gate dielectric layer on the first two-dimensional (2D) channel layer;
forming disposable filler sections between the dielectric support bridges;
removing portions of the first gate dielectric layer on exposed sides of the first two-dimensional (2D) channel layer; and
forming a second two-dimensional (2D) channel layer within the portions along a second side of the first two-dimensional (2D) channel layer to form a vertical rippled profile.