| CPC H01L 29/66553 (2013.01) [H01L 21/823431 (2013.01); H01L 21/823821 (2013.01); H01L 27/0886 (2013.01); H01L 29/42392 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/78696 (2013.01); H01L 21/823468 (2013.01)] | 20 Claims |
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7. A method comprising:
forming a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising alternating layers of a first semiconductor material and a second semiconductor material different from the first semiconductor material;
etching sidewalls of the layers of the first semiconductor material to form sidewall recesses;
depositing a plurality of spacer layers on sidewalls of the layers of the first semiconductor material;
performing a first etch process to etch the plurality of spacer layers and to form inner spacers, wherein a first spacer layer of the plurality of spacer layers has a lower etch rate than a second spacer layer of the plurality of spacer layers, wherein the first spacer layer is closer to the layers of the first semiconductor material than the second spacer layer, wherein a third spacer layer of the plurality of spacer layers has a lower etch rate than the second spacer layer of the plurality of spacer layers, wherein the second spacer layer is closer to the layers of the first semiconductor material than the third spacer layer;
performing a second etch process to remove the layers of the first semiconductor material and form first recesses extending between the layers of the second semiconductor material, wherein the second etch process etches the inner spacers at an etching rate less than an etching rate of the first semiconductor material; and
forming gate structures in the first recesses.
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