| CPC H01L 29/42392 (2013.01) [H01L 27/092 (2013.01); H01L 29/0665 (2013.01); H01L 29/78696 (2013.01)] | 7 Claims |
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1. A semiconductor integrated circuit device including standard cells arranged in a first direction,
in each of the standard cells, a p-type region in which p-type transistors are formed and an n-type region in which n-type transistors are formed being disposed adjacently in a second direction vertical to the first direction, the standard cell comprising:
a first nanosheet group including two or more nanosheets, each extending in the first direction, arranged in the second direction in the p-type region;
a second nanosheet group including two or more nanosheets, each extending in the first direction, arranged in the second direction in the n-type region;
a first gate interconnect extending in the second direction, formed to surround peripheries of the nanosheets of the first nanosheet group in the second direction and a third direction perpendicular to the first and second directions; and
a second gate interconnect extending in the second direction, formed to surround peripheries of the nanosheets of the second nanosheet group in the second and third directions,
wherein
in the first nanosheet group, a first nanosheet farthest from the n-type region has a face exposed from the first gate interconnect on a side away from the n-type region in the second direction, and a second nanosheet closest to the n-type region has a face exposed from the first gate interconnect on a side closer to the n-type region in the second direction, and
in the second nanosheet group, a third nanosheet farthest from the p-type region has a face exposed from the second gate interconnect on a side away from the p-type region in the second direction, and a fourth nanosheet closest to the p-type region has a face exposed from the second gate interconnect on a side closer to the p-type region in the second direction.
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