	US 12,249,636 B2
	Tuning gate lengths in multi-gate field effect transistors
Chia-Hao Pao, Kaohsiung (TW); Chih-Chuan Yang, Hsinchu (TW); Shih-Hao Lin, Hsinchu (TW); Kian-Long Lim, Hsinchu (TW); Chih-Hsuan Chen, Hsinchu (TW); and Ping-Wei Wang, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Dec. 10, 2021, as Appl. No. 17/548,133.
Claims priority of provisional application 63/178,725, filed on Apr. 23, 2021.
Prior Publication US 2022/0344484 A1, Oct. 27, 2022
Int. Cl. H01L 29/423 (2006.01); H01L 21/265 (2006.01); H01L 21/308 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)

CPC H01L 29/42392 (2013.01) [H01L 21/26513 (2013.01); H01L 21/308 (2013.01); H01L 29/0665 (2013.01); H01L 29/401 (2013.01); H01L 29/41775 (2013.01); H01L 29/66553 (2013.01); H01L 29/78696 (2013.01)]

20 Claims

1. A method, comprising:

providing a substrate having a first region and a second region;

forming a fin protruding from the first region of the substrate, wherein the fin includes a first SiGe layer and a stack of alternating Si layers and second SiGe layers disposed over the first SiGe layer, and wherein the first SiGe layer has a first concentration of Ge and each of the second SiGe layers has a second concentration of Ge that is greater than the first concentration;

recessing the fin to form a source/drain (S/D) recess;

recessing the first SiGe layer and the second SiGe layers exposed in the S/D recess in a same lateral etching process, wherein the second SiGe layers are laterally recessed more than the first SiGe layer due to each of the second SiGe layers having the second concentration of Ge that is greater than the first concentration;

forming an S/D feature in the S/D recess;

removing the recessed first SiGe layer and the second SiGe layers to form openings; and

forming a metal gate structure over the fin and in the openings.