US 12,249,634 B2
Vertical-conduction silicon carbide MOSFET device having improved gate biasing structure and manufacturing process thereof
Mario Giuseppe Saggio, Aci Bonaccorsi (IT); Alfio Guarnera, Trecastagni (IT); and Cateno Marco Camalleri, Catania (IT)
Assigned to STMICROELECTRONICS S.r.l., Agrate Brianza (IT)
Filed by STMICROELECTRONICS S.r.l., Agrate Brianza (IT)
Filed on Feb. 10, 2022, as Appl. No. 17/669,239.
Claims priority of application No. 102021000003653 (IT), filed on Feb. 17, 2021.
Prior Publication US 2022/0262913 A1, Aug. 18, 2022
Int. Cl. H01L 29/423 (2006.01); H01L 29/16 (2006.01); H01L 29/40 (2006.01); H01L 29/43 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/42376 (2013.01) [H01L 29/1608 (2013.01); H01L 29/401 (2013.01); H01L 29/435 (2013.01); H01L 29/66068 (2013.01); H01L 29/7827 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A vertical-conduction MOSFET device comprising:
a body of silicon carbide having a first and a second face and a peripheral zone, the body including:
a first current conduction region, of a first conductivity type, extending in the body from the second face and having a superficial portion facing the first face;
a body region, of a second conductivity type, extending in the body from the first face; and
a second current conduction region, of the first conductivity type, extending to an inside of the body region from the first face of the body;
an insulated gate region, extending on the first face of the body and overlying a portion of the body region laterally between the first current conduction region and the second current conduction region, the insulated gate region comprising a gate conductive region; and
a surface edge structure, extending on the first face of the body, in the peripheral zone of the body, the surface edge structure including an oxide layer, a passivation layer, and an annular connection region, of a conductive material,
wherein the gate conductive region and the annular connection region each including a silicon layer and a metal silicide layer overlying the silicon layer,
the gate conductive region includes a gate semiconductor portion including the silicon layer and a gate metal portion including the metal silicide layer,
the annular connection region includes a semiconductor connection portion including the silicon layer and a metal connection portion including the metal silicide layer,
first portions of the semiconductor connection portion and the metal connection portion extend on the first face of the body, and second portions of the semiconductor connection portion and the metal connection portion are spaced from the first face of the body by the oxide layer, and
the passivation layer is on the first portions and the second portions of the semiconductor connection portion and the metal connection portion.