US 12,249,633 B2
Field-effect transistor and method for manufacturing field-effect transistor
Nobuyuki Shirai, Yokohama (JP); and Nobuyoshi Matsuura, Yokohama (JP)
Assigned to WILL SEMICONDUCTOR (SHANGHAI) CO. LTD., Shanghai (CN)
Filed by WILL SEMICONDUCTOR (SHANGHAI) CO. LTD., Shanghai (CN)
Filed on Feb. 9, 2022, as Appl. No. 17/667,641.
Claims priority of application No. 2021-151414 (JP), filed on Sep. 16, 2021.
Prior Publication US 2023/0079309 A1, Mar. 16, 2023
Int. Cl. H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/4236 (2013.01) [H01L 29/66734 (2013.01); H01L 29/7813 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A field-effect transistor, comprising:
a trench, which is formed in a semiconductor substrate;
an oxide insulating layer, which is accommodated inside the trench, the oxide insulating layer having a surface with a convex shape;
a shield gate region, which is disposed at a lower part in the oxide insulating layer;
a gate region, which is disposed above the shield gate region in the oxide insulating layer with an interval therebetween, wherein the gate region has a bottom surface with a convex shape, and the surface of the oxide insulating layer with the convex shape matches the bottom surface of the gate region with the convex shape; and
a nitride insulating layer, which is disposed in a way of covering a bottom and a surrounding of a lateral side of the shield gate region in the oxide insulating layer with an interval therebetween;
wherein a thickness of the oxide insulating layer that is closer to an inner side than a line extending upward from an outer peripheral side of the nitride insulating layer is ½ of a thickness of the nitride insulating layer or more; or a thickness of the oxide insulating layer between an upper end of the nitride insulating layer and the gate region is ½ of a thickness of the nitride insulating layer or more.