US 12,249,632 B2
Semiconductor memory device, method of manufacturing the same, and electronic device including the same
Huilong Zhu, Poughkeepsie, NY (US)
Assigned to INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES, Beijing (CN)
Filed by INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES, Beijing (CN)
Filed on Dec. 12, 2022, as Appl. No. 18/064,449.
Application 18/064,449 is a division of application No. 16/123,016, filed on Sep. 6, 2018, granted, now 11,626,498.
Claims priority of application No. 201710800421.6 (CN), filed on Sep. 6, 2017.
Prior Publication US 2023/0110504 A1, Apr. 13, 2023
Int. Cl. H10B 12/00 (2023.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/739 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/30 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/30 (2023.01); H10B 51/10 (2023.01); H10B 51/20 (2023.01); H10B 51/30 (2023.01); H01L 27/12 (2006.01)
CPC H01L 29/42356 (2013.01) [H01L 29/66666 (2013.01); H01L 29/7391 (2013.01); H01L 29/7827 (2013.01); H01L 29/78642 (2013.01); H10B 12/0335 (2023.02); H10B 12/05 (2023.02); H10B 12/30 (2023.02); H10B 12/315 (2023.02); H10B 12/482 (2023.02); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/30 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/30 (2023.02); H10B 51/10 (2023.02); H10B 51/20 (2023.02); H10B 51/30 (2023.02); H01L 27/1203 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor memory device, comprising:
providing a stack of a sacrificial layer, a first source/drain layer, a channel layer, and a second source/drain layer on a substrate;
defining a plurality of pillar-shaped active regions arranged in rows and columns in the first source/drain layer, the channel layer, and the second source/drain layer;
after defining the plurality of pillar-shaped active regions, removing the sacrificial layer and forming a plurality of bit lines extending below the respective columns of active regions in a space left by the removal of the sacrificial layer;
forming gate stacks around peripheries of the channel layer in the respective active regions; and
forming a plurality of word lines between the respective rows of active regions, wherein each of the word lines is electrically connected to the gate stacks of the respective memory cells in a corresponding one of the rows.