US 12,249,629 B2
Field plate structure for high voltage device
Chia-Cheng Ho, Hsinchu (TW); Hui-Ting Lu, Zhudong Township (TW); Pei-Lun Wang, Zhubei (TW); Yu-Chang Jong, Hsinchu (TW); and Jyun-Guan Jhou, Taoyuan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on May 3, 2022, as Appl. No. 17/735,369.
Application 16/952,438 is a division of application No. 16/417,735, filed on May 21, 2019, granted, now 10,861,946, issued on Dec. 8, 2020.
Application 17/735,369 is a continuation of application No. 16/952,438, filed on Nov. 19, 2020, granted, now 11,335,784.
Prior Publication US 2022/0262908 A1, Aug. 18, 2022
Int. Cl. H01L 29/40 (2006.01); H01L 21/28 (2006.01); H01L 21/765 (2006.01); H01L 21/82 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/402 (2013.01) [H01L 21/28088 (2013.01); H01L 21/765 (2013.01); H01L 21/823842 (2013.01); H01L 27/0922 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01); H01L 29/66681 (2013.01); H01L 29/7816 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a gate electrode disposed on a substrate between a pair of source/drain regions;
a dielectric layer over the substrate; and
a field plate disposed on the dielectric layer and laterally between the gate electrode and a first source/drain region in the pair of source/drain regions, wherein the field plate comprises a first field plate layer and a second field plate layer, wherein the second field plate layer extends along sidewalls and a bottom surface of the first field plate layer, wherein the first and second field plate layers comprise a conductive material, wherein a top surface of the field plate is aligned with a top surface of the gate electrode.