US 12,249,626 B2
Arsenic diffusion profile engineering for transistors
Patricia M. Liu, Saratoga, CA (US); Flora Fong-Song Chang, Saratoga, CA (US); and Zhiyuan Ye, San Jose, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Appl. No. 17/628,634
Filed by Applied Materials, Inc., Santa Clara, CA (US)
PCT Filed Jul. 1, 2020, PCT No. PCT/US2020/040535
§ 371(c)(1), (2) Date Jan. 20, 2022,
PCT Pub. No. WO2021/021381, PCT Pub. Date Feb. 4, 2021.
Claims priority of provisional application 62/881,710, filed on Aug. 1, 2019.
Prior Publication US 2022/0320294 A1, Oct. 6, 2022
Int. Cl. H01L 21/00 (2006.01); H01L 21/02 (2006.01); H01L 21/22 (2006.01); H01L 29/167 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/167 (2013.01) [H01L 21/02463 (2013.01); H01L 21/2205 (2013.01); H01L 29/66803 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A transistor, comprising:
a gate electrode structure disposed over a channel region;
a source/drain extension region doped with arsenic disposed adjacent to the channel region;
an epitaxial arsenic doped silicon layer disposed on the source/drain extension region; and
an epitaxial source/drain region disposed on the epitaxial arsenic doped silicon layer, the arsenic doped silicon layer disposed between the source/drain region and the source/drain extension region.