CPC H01L 29/0673 (2013.01) [H01L 21/823468 (2013.01); H01L 29/42392 (2013.01); H01L 29/6656 (2013.01); H01L 29/66742 (2013.01); H01L 29/7848 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] | 20 Claims |
1. A semiconductor device, comprising:
a plurality of nanostructures on a substrate;
a source/drain region in contact with the plurality of nanostructures; and
a gate structure, comprising:
a first portion formed between each nanostructure of the plurality of nanostructures;
a plurality of inner spacers, wherein an inner spacer of the plurality of inner spacers is disposed between adjacent nanostructures of the plurality of nanostructures; and
a second portion formed under a bottom-most nanostructure of the plurality of nanostructures and extending under a top surface of the substrate, wherein the second portion extends laterally under a bottom-most inner spacer of the plurality of inner spacers and is in contact with a bottom surface of the bottom-most inner spacer.
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