US 12,249,623 B2
Semiconductor devices having parasitic channel structures
Yu-Cheng Shen, Hsinchu (TW); and Guan-Jie Shen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Sep. 8, 2021, as Appl. No. 17/447,099.
Claims priority of provisional application 63/175,706, filed on Apr. 16, 2021.
Prior Publication US 2022/0336585 A1, Oct. 20, 2022
Int. Cl. H01L 29/423 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/0673 (2013.01) [H01L 21/823468 (2013.01); H01L 29/42392 (2013.01); H01L 29/6656 (2013.01); H01L 29/66742 (2013.01); H01L 29/7848 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a plurality of nanostructures on a substrate;
a source/drain region in contact with the plurality of nanostructures; and
a gate structure, comprising:
a first portion formed between each nanostructure of the plurality of nanostructures;
a plurality of inner spacers, wherein an inner spacer of the plurality of inner spacers is disposed between adjacent nanostructures of the plurality of nanostructures; and
a second portion formed under a bottom-most nanostructure of the plurality of nanostructures and extending under a top surface of the substrate, wherein the second portion extends laterally under a bottom-most inner spacer of the plurality of inner spacers and is in contact with a bottom surface of the bottom-most inner spacer.