US 12,249,622 B2
Nanoribbon thick gate devices with differential ribbon spacing and width for SOC applications
Tanuj Trivedi, Hillsboro, OR (US); Rahul Ramaswamy, Portland, OR (US); Jeong Dong Kim, Scappoose, OR (US); Ting Chang, Portland, OR (US); Walid M. Hafez, Portland, OR (US); Babak Fallahazad, Portland, OR (US); Hsu-Yu Chang, Hillsboro, OR (US); and Nidhi Nidhi, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 13, 2019, as Appl. No. 16/713,684.
Prior Publication US 2021/0184001 A1, Jun. 17, 2021
Int. Cl. H01L 29/786 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); B82Y 40/00 (2011.01)
CPC H01L 29/0673 (2013.01) [H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/785 (2013.01); B82Y 40/00 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a plurality of first semiconductor layers in a vertical stack over the substrate, wherein the first semiconductor layers have a first spacing;
a first dielectric surrounding each of the first semiconductor layers, wherein the first dielectric has a first thickness;
a plurality of second semiconductor layers in a vertical stack over the substrate, wherein the second semiconductor layers have a second spacing that is greater than the first spacing, wherein each one of the plurality of second semiconductor layers has a thickness different than a thickness of each one of the plurality of first semiconductor layers, wherein each one of the plurality of second semiconductor layers has a width different than a width of each one of the plurality of first semiconductor layers, and wherein individual ones of the plurality of second semiconductor layers are staggered with corresponding individual ones of the plurality of first semiconductor layers; and
a second dielectric surrounding each of the second semiconductor layers, wherein the second dielectric has a second thickness that is greater than the first thickness.