US 12,249,611 B2
Imaging device, electronic device, and signal processing method with pixel array and memory array respectively on first and second substrates
Daisuke Saito, Kanagawa (JP); and Katsuhiko Hanzawa, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Appl. No. 18/263,042
Filed by Sony Semiconductor Solutions Corporation, Kanagawa (JP)
PCT Filed Jan. 18, 2022, PCT No. PCT/JP2022/001540
§ 371(c)(1), (2) Date Jul. 26, 2023,
PCT Pub. No. WO2022/190644, PCT Pub. Date Sep. 15, 2022.
Claims priority of application No. 2021-036638 (JP), filed on Mar. 8, 2021.
Prior Publication US 2024/0088175 A1, Mar. 14, 2024
Int. Cl. H01L 27/146 (2006.01); G06F 17/15 (2006.01); H04N 25/77 (2023.01); H04N 25/771 (2023.01); H04N 25/772 (2023.01); H04N 25/778 (2023.01); H04N 25/78 (2023.01); H04N 25/79 (2023.01)
CPC H01L 27/14605 (2013.01) [G06F 17/153 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H01L 27/14641 (2013.01); H04N 25/77 (2023.01); H04N 25/771 (2023.01); H04N 25/772 (2023.01); H04N 25/778 (2023.01); H04N 25/78 (2023.01); H04N 25/79 (2023.01)] 18 Claims
OG exemplary drawing
 
1. An imaging device comprising:
a first substrate on which a pixel array that outputs a pixel signal obtained by photoelectrically converting incident light in a first direction is arranged; and
a second substrate on which a memory array that outputs a convolution signal indicating a result of a product-sum operation of an input signal based on the pixel signal in a second direction is arranged, wherein the first substrate and the second substrate at least partially overlap each other;
a pixel control circuit that controls the pixel array;
a pixel signal processing circuit that processes the pixel signal read from the pixel array;
a computer in memory (CIM) input control circuit that controls the memory array; and
a CIM read circuit that processes the convolution signal read from the memory array, wherein
on the second substrate, the pixel control circuit and the CIM read circuit are arranged so as to be opposed to each other with the memory array interposed between the pixel control circuit and the CIM read circuit, and
the pixel signal processing circuit and the CIM input control circuit are arranged so as to be opposed to each other with the memory array interposed between the pixel signal processing circuit and the CIM input control circuit.