US 12,249,608 B2
Method for manufacturing semiconductor structure and semiconductor structure thereof
Yun-Feng Kao, New Taipei (TW); and Katherine H. Chiang, New Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Apr. 25, 2022, as Appl. No. 17/728,785.
Prior Publication US 2023/0343789 A1, Oct. 26, 2023
Int. Cl. H01L 27/12 (2006.01); H01L 21/822 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); G11C 11/40 (2006.01)
CPC H01L 27/1207 (2013.01) [H01L 21/8221 (2013.01); H01L 23/528 (2013.01); G11C 11/40 (2013.01); H01L 23/5226 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
an interconnection structure, including a first metal line layer, a second metal line layer and a third metal line layer arranged over one another;
a first transistor, including a gate structure; and
a second transistor, disposed adjacent to the first transistor, and including a source/drain structure,
wherein the gate structure of the first transistor is disposed over and electrically connected to the first metal line layer, and the source/drain structure of the second transistor is arranged below and electrically connected to the third metal line layer through the second metal line layer,
wherein the first metal line layer and the third metal line layer are disposed within an array
area of the semiconductor structure, and the second metal line layer includes an elongated metal line that extends to a peripheral area of the semiconductor structure outside the array area.