US 12,249,606 B2
Integrated circuit device
Minhee Choi, Suwon-si (KR); Keunhwi Cho, Seoul (KR); Myunggil Kang, Suwon-si (KR); Seokhoon Kim, Suwon-si (KR); Dongwon Kim, Seongnam-si (KR); Pankwi Park, Incheon (KR); and Dongsuk Shin, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jan. 16, 2024, as Appl. No. 18/414,039.
Application 18/414,039 is a continuation of application No. 18/122,253, filed on Mar. 16, 2023, granted, now 11,948,942.
Application 18/122,253 is a continuation of application No. 17/231,114, filed on Apr. 15, 2021, granted, now 11,631,674, issued on Apr. 18, 2023.
Claims priority of application No. 10-2020-0101392 (KR), filed on Aug. 12, 2020.
Prior Publication US 2024/0153954 A1, May 9, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/092 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/161 (2006.01); H01L 29/167 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0924 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02579 (2013.01); H01L 21/0262 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/161 (2013.01); H01L 29/167 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66795 (2013.01); H01L 29/775 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing an integrated circuit device, the method comprising:
forming a structure including a fin-type active region and a pair of nanosheet stacks, the fin-type active region extending lengthwise in a first horizontal direction, each of the pair of nanosheet stacks including a plurality of nanosheets which overlap each other in a vertical direction on a fin top of the fin-type active region; and
forming a source/drain area between the pair of nanosheet stacks on the fin-type active region, the forming of the source/drain area comprising:
forming an outer blocking layer;
forming an inner blocking layer on the outer blocking layer; and
forming a main body layer on the inner blocking layer,
wherein each of the outer blocking layer and the main body layer includes a Si1-xGex layer, where x≠0, and the inner blocking layer includes a Si layer, and
wherein the inner blocking layer has a width greater than a width of the outer blocking layer.