US 12,249,604 B2
Semiconductor device having doped work function metal layer
Chih-Hsiung Huang, Kaohsiung (TW); Chung-En Tsai, Hsinchu County (TW); Chee-Wee Liu, Taipei (TW); Kun-Wa Kuok, Hsinchu (TW); and Yi-Hsiu Hsiao, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW); and NATIONAL TAIWAN UNIVERSITY, Taipei (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW); and NATIONAL TAIWAN UNIVERSITY, Taipei (TW)
Filed on Jul. 27, 2023, as Appl. No. 18/360,416.
Application 17/585,020 is a division of application No. 16/548,730, filed on Aug. 22, 2019, granted, now 11,244,945, issued on Feb. 8, 2022.
Application 18/360,416 is a continuation of application No. 17/585,020, filed on Jan. 26, 2022, granted, now 11,791,338.
Prior Publication US 2023/0369331 A1, Nov. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/40 (2006.01); H01L 21/28 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01)
CPC H01L 27/092 (2013.01) [H01L 21/28088 (2013.01); H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 27/0924 (2013.01); H01L 29/401 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate having an N-type region;
a gate stack over the N-type region of the substrate and comprising:
a gate dielectric layer;
a bottom work function (WF) metal layer over the gate dielectric layer;
a top WF metal layer over and in contact with the bottom WF metal layer, wherein dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the top WF metal layer to the bottom WF metal layer; and
a filling metal over the top WF metal layer; and
epitaxy structures over the N-type region of the substrate and on opposite sides of the gate stack.