US 12,249,602 B2
Electrostatic discharge protection circuit
Krishna Praveen Mysore Rajagopal, Santa Clara, CA (US); and Mariano Dissegna, Plano, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Aug. 10, 2021, as Appl. No. 17/398,115.
Application 17/398,115 is a division of application No. 16/393,850, filed on Apr. 24, 2019, granted, now 11,107,806.
Prior Publication US 2021/0366896 A1, Nov. 25, 2021
Int. Cl. H01L 27/02 (2006.01); H01L 27/06 (2006.01); H02H 9/04 (2006.01); H01L 29/78 (2006.01); H01L 29/80 (2006.01); H01L 49/02 (2006.01)
CPC H01L 27/0266 (2013.01) [H01L 27/0629 (2013.01); H02H 9/046 (2013.01); H01L 28/20 (2013.01); H01L 29/78 (2013.01); H01L 29/80 (2013.01)] 16 Claims
OG exemplary drawing
 
12. A method of forming an integrated circuit comprising:
providing a metal-oxide-semiconductor field-effect transistor (MOSFET) extending into a semiconductor substrate, the MOSFET having a drain coupled to a protected node, a gate, and a source coupled to a circuit ground;
electrically connecting a first current handling terminal of a junction field-effect transistor (JFET) directly to the drain of the MOSFET, electrically connecting a second current handling terminal of the JFET to the gate of the MOSFET, and electrically coupling a control terminal of the JFET to a reference potential, wherein the JFET is configured to be on when a first voltage on the control terminal of the JFET is less than a second voltage on the first current handling terminal of the JFET; and
electrically connecting the second current handling terminal of the JFET is to a first terminal of a resistor, and electrically connecting a second terminal of the resistor to the circuit ground.