US 12,249,601 B2
Integrated circuit device, method, layout, and system
Po-Zeng Kang, Hsin-Hua (TW); Wen-Shen Chou, Zhubei (TW); and Yung-Chow Peng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Jul. 29, 2020, as Appl. No. 16/942,264.
Prior Publication US 2022/0037312 A1, Feb. 3, 2022
Int. Cl. H01L 27/06 (2006.01); G06F 30/392 (2020.01); G06F 30/3953 (2020.01); H01L 23/522 (2006.01); H01L 27/02 (2006.01); H03K 19/0944 (2006.01)
CPC H01L 27/0207 (2013.01) [G06F 30/392 (2020.01); G06F 30/3953 (2020.01); H01L 23/5226 (2013.01); H01L 27/0629 (2013.01); H03K 19/09441 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device comprising:
a transistor comprising:
a first gate structure extending in a first direction between first and second active areas;
a first source/drain (S/D) metal portion extending in the first direction and overlying the first active area; and
a second S/D metal portion extending in the first direction and overlying the second active area;
a second gate structure extending in the first direction;
a load resistor comprising a third S/D metal portion extending parallel to the second gate structure, adjacent to the second gate structure in a second direction perpendicular to the first direction, and positioned directly on a dielectric layer and in a same layer as the first and second S/D metal portions,
wherein the first through third S/D metal portions comprise a same conductive material composition and a same height in a third direction perpendicular to the first and second directions;
a first via overlying the first S/D metal portion;
second and third vias overlying the third S/D metal portion; and
a first conductive structure configured to electrically connect the first via to the second via.