US 12,249,593 B2
Electronic device
Yoichiro Kurita, Tokyo (JP)
Assigned to NAGASE & CO., LTD., Osaka (JP)
Filed by NAGASE & CO., LTD., Osaka (JP)
Filed on Sep. 14, 2023, as Appl. No. 18/368,078.
Application 16/591,797 is a division of application No. 16/029,194, filed on Jul. 6, 2018, granted, now 10,475,767, issued on Nov. 12, 2019.
Application 18/368,078 is a continuation of application No. 17/216,621, filed on Mar. 29, 2021, granted, now 11,791,311.
Application 17/216,621 is a continuation of application No. 16/591,797, filed on Oct. 3, 2019, granted, now 10,991,673, issued on Apr. 27, 2021.
Claims priority of application No. 2018-000065 (JP), filed on Jan. 4, 2018; application No. 2018-109356 (JP), filed on Jun. 7, 2018; and application No. 2018-128380 (JP), filed on Jul. 5, 2018.
Prior Publication US 2023/0420417 A1, Dec. 28, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2023.01); G11C 5/04 (2006.01); H01L 23/498 (2006.01); G06N 3/04 (2023.01); H01L 25/10 (2006.01)
CPC H01L 25/0652 (2013.01) [G11C 5/04 (2013.01); H01L 23/49833 (2013.01); G06N 3/04 (2013.01); H01L 25/105 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06531 (2013.01); H01L 2225/06534 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/06572 (2013.01); H01L 2225/06593 (2013.01)] 9 Claims
OG exemplary drawing
 
1. An electronic device, comprising:
an interconnect layer;
a second chip and a third chip provided on a first side of the interconnect layer; and
a first chip provided on a second side of the interconnect layer, wherein
the first chip includes a first memory element connected to the second chip,
the second chip includes a logic element,
the third chip includes a second memory element connected to the second chip,
the first chip further includes a memory controller connected to the first memory element and the second memory element,
the interconnect layer includes conductive members connecting between the first chip and
the second chip, and connecting between the first chip and the third chip, respectively, and
the interconnect layer does not include a conductive member directly connecting between the second chip and the third chip.