US 12,249,586 B2
Film structure for bond pad
Julie Yang, Hsin-Chu (TW); Chii Ming Wu, Taipei (TW); Tzu-Chung Tsai, Hsinchu County (TW); and Yao-Wen Chang, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Apr. 26, 2022, as Appl. No. 17/729,363.
Application 17/729,363 is a division of application No. 16/589,497, filed on Oct. 1, 2019, granted, now 11,322,464.
Prior Publication US 2022/0254744 A1, Aug. 11, 2022
Int. Cl. H01L 29/78 (2006.01); H01L 23/00 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 24/05 (2013.01) [H01L 24/03 (2013.01); H01L 24/13 (2013.01); H01L 2224/02206 (2013.01); H01L 2224/02215 (2013.01); H01L 2224/03019 (2013.01); H01L 2224/03614 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/13026 (2013.01); H01L 2924/04941 (2013.01); H01L 2924/05432 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
an interconnect structure disposed over a substrate, wherein the interconnect structure comprises a plurality of interconnect layers disposed within a dielectric structure;
a bond pad structure disposed over the interconnect structure, wherein the bond pad structure comprises a contact layer;
a first masking layer comprising a metal-oxide disposed over the bond pad structure, the first masking layer having interior sidewalls and having a bottommost surface arranged directly over a top surface of the bond pad structure, the interior sidewalls forming an opening extending through the first masking layer;
a second masking layer disposed over the first masking layer and along sidewalls of the bond pad structure, wherein the second masking layer vertically extends below the bottommost surface of the first masking layer; and
a conductive bump arranged within the opening and on the contact layer.