US 12,249,580 B2
Passivation scheme design for wafer singulation
Hsien-Wei Chen, Hsinchu (TW); Ying-Ju Chen, Tuku Township (TW); and Ming-Fa Chen, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 25, 2023, as Appl. No. 18/358,530.
Application 18/358,530 is a division of application No. 17/883,932, filed on Aug. 9, 2022, granted, now 11,942,436.
Application 17/883,932 is a division of application No. 17/006,365, filed on Aug. 28, 2020, granted, now 11,699,663, issued on Jul. 11, 2023.
Claims priority of provisional application 63/015,780, filed on Apr. 27, 2020.
Prior Publication US 2023/0369238 A1, Nov. 16, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 21/74 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01); H01L 23/525 (2006.01); H01L 23/544 (2006.01); H01L 23/58 (2006.01)
CPC H01L 23/544 (2013.01) [H01L 21/74 (2013.01); H01L 21/78 (2013.01); H01L 23/3171 (2013.01); H01L 23/525 (2013.01); H01L 23/562 (2013.01); H01L 23/585 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate;
electrical components in the substrate;
an interconnect structure over the substrate and electrically coupled to the electrical components;
a seal ring in the interconnect structure;
a conductive pad over and electrically coupled to the interconnect structure;
a first passivation layer over the conductive pad and the interconnect structure, wherein the first passivation layer covers a peripheral portion of the conductive pad and exposes a center portion of the conductive pad; and
a first dielectric layer over the first passivation layer, wherein the first dielectric layer covers the center portion of the conductive pad, wherein a first sidewall of the first passivation layer is disposed laterally between the seal ring and a sidewall of the first dielectric layer, wherein the sidewall of the first dielectric layer is aligned with a sidewall of the substrate along a same line.