US 12,249,577 B2
Cap structure for interconnect dielectrics and methods of fabrication
Shashi Vyas, Hillsboro, OR (US); Sudipto Naskar, Portland, OR (US); and Charles Wallace, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 17, 2020, as Appl. No. 17/125,680.
Prior Publication US 2022/0199544 A1, Jun. 23, 2022
Int. Cl. H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/53295 (2013.01) [H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a first interconnect level comprising a first dielectric between a pair of interconnect structures comprising uppermost surfaces; and
a second interconnect level above the first interconnect level, the second interconnect level comprising:
a cap structure comprising a second dielectric over the first dielectric, the cap structure comprising a top surface and a sidewall surface;
a liner comprising a third dielectric on the top surface and on the sidewall surface, but absent from at least a portion of the uppermost surfaces; and
a fourth dielectric over at least a portion of the liner and over the portion of the uppermost surfaces.